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FPGA Compute Processing Technologies and Workflows
May 17, 2018 @ 6:00 PM - 9:00 PM
Co-sponsored by: email@example.com
Presentation Focus: Evolution of FPGA Compute Hardware, Algorithm development and Programming Methodologies.
Beginning with the inclusion of simple multiplier blocks at the 130nM process node, FPGA compute hardware solutions have continually evolved becoming more capable, flexible, and scalable with each generation. These embedded compute elements, together with high density RAM elements, flexible logic modules, and ubiquitous interconnect support implementation of extremely compute intensive algorithms in a power efficient manner.
Growing FPGA compute capabilities provide more options for implementation and more options to manage data flow and for partitioning complex compute operations between hardware and software. Algorithm Developers, Software Programmers, Embedded Programmers and FPGA Hardware Engineers can all contribute to this process and tool chains are evolving to support this collaboration. Complex systems also must be verified which drives the need for a more unified flow that supports all phases of the development process. Higher level tools have evolved to the point where there are several alternatives from which to choose.
Speaker(s): Mark Moyer,
6:00-6:30 pm Networking Time
6:30-6:45 business Meeting
6:45 -8:30 Main Presentation
Room: Deveraux Room
Bldg: Rialto Center, 2nd Floor
228 East 4th Street